1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device, and more particularly, to a programming method employable by a multi-bit flash memory device.
2. Description of the Related Art
Semiconductor memory devices are generally classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. Volatile semiconductor memory devices have a relatively fast read/write speed, but lose stored data when external power supply is interrupted. Nonvolatile semiconductor memory devices retain stored data even without external power supply. Therefore, nonvolatile semiconductor memory devices are used to store data that must be retained regardless of power supply. Examples of the nonvolatile semiconductor memory devices include a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electrically erasable programmable read-only memory (EEPROM).
In general, since erase and write operations are relatively difficult with the MROMs, PROMs, and EPROMs, common users may not be able to update memory data. Erase and write operations may be electrically implemented with EEPROMs. Thus, EEPROMS are generally more widely used in system programming or auxiliary memory devices, which require continuous updating. Flash EEPROMs generally have a higher degree of integration than other types of EEPROMs. Thus, flash EEPROMs may be advantageous for high-capacity auxiliary memory devices. More particularly, a NAND-type flash EEPROM (hereinafter, referred to as a NAND flash memory) may generally enable a higher degree of integration than other types flash EEPROMs.
When 1-bit data is stored in a memory cell, the memory cell has one of two threshold voltage distributions corresponding to data ‘1’ and data ‘0’. On the other hand, when 2-bit data is stored in a memory cell, the memory cell is programmed to a threshold voltage included in one of four threshold voltage distributions. Likewise, when 3-bit data is stored in a memory cell, the memory cell is programmed to a threshold voltage included in one of eight threshold voltage distributions. Various technologies for storing 4-bit data in one memory cell are being developed.
In general, a memory cell storing multi-bit data has one of a plurality of threshold voltage states. Therefore, it is difficult to provide a sufficient read margin between threshold voltage states in a multi-bit flash memory device using general program schemes and general circuit technologies. A multi-bit flash memory cell may have 2k threshold voltage states corresponding to k bits stored within the limited threshold voltage range. That is, a multi-bit flash memory cell may be programmed densely in order to include 2k threshold voltage states corresponding to k bits stored within the limited threshold voltage range. Thus, an interval (i.e., a read margin) between threshold voltage states of the multi-bit flash memory cell must be reduced.
For example, for storing 4-bit data, a threshold voltage distribution of each program operation in a multi-bit memory cell may have 16 threshold voltage states. For programming of 4-bit data, data may be sequentially input into a memory cell on a 4-page basis. More particularly, e.g., after third page data is programmed, the memory cell may have one of eight threshold voltage distributions 0 to 7. The fourth page data may be programmed to threshold voltage distributions corresponding to bit values of the fourth page data through the threshold voltage distributions 0 to 7 resulting from the programming of the third page data. After programming of the third page data, if the fourth page data corresponds to logic ‘1’, the memory cell may be set to be Program Inhibit. A threshold voltage of the memory cell set to be Program Inhibit may not change after the programming of the fourth page data. On the other hand, if the fourth page data is logic ‘0’, a threshold voltage of the memory cell may be programmed to a state 8. In this way, when the fourth page data is logic ‘0’, threshold voltages of memory cells, which belong respectively to the threshold voltage states 0 to 7 after programming third page data, respectively change into threshold voltage states 8 to 15 through a programming operation.
After the program operation, the memory cells programmed to the threshold voltage states 8 to 15 may be program-verified. Program-verify operations may be performed in the arrangement order of the threshold voltage states 8 to 15. For example, verify read operations may be sequentially performed to detect whether the memory cells are programmed to the states 10 to 15. The memory cells, determined to be Program Pass through the verify read operation for each state, may be set to be Program Inhibit. The memory cells, determined to be Program Fail through the verify read operation, may be set to be reprogrammed.
FIG. 1 illustrates a diagram of a problem of charge loss that may occur during a programming operation of a multi-bit memory cell.
FIG. 1 illustrates threshold voltage distributions 30 and 35 created by programming of third page data and threshold voltage distributions 40 and 60 created by programming of fourth page data. In a normal case, the threshold voltage distribution 55 should be created in the form of a threshold voltage distribution 50. However, a flash memory device may include a memory cell that has defects in an insulating layer between a channel and a floating gate. Also, the threshold voltage of a memory cell may be reduced due to the charge loss of the floating gate by degradation or hot temperature stress (HTS).
Thus, rather than the normal threshold voltage distribution 50, the abnormal threshold voltage distribution 55 may be created by the programming of the third page data. In particular, due to the charge loss, there may be a memory cell whose threshold voltage is reduced below a first verify voltage Vpre2 corresponding to a state 9. Such a memory cell has a threshold voltage included in a distribution 70. A memory cell whose third page data is programmed to the threshold voltage corresponding to the distribution 70 may have a 2-bit error after the programming of the fourth page data. That is, the memory cells corresponding to the distribution 70 include memory cells that should be programmed to data ‘0101’ according to the programming of the fourth page data. However, during the program operation of the fourth page data, the memory cells included in the distribution 70 may be set to be Program Inhibit after a one-time program loop. That is, because the memory cells included in the distribution 70 have a threshold voltage between the first verify voltage Vpre2 and the second verify voltage Vfy2, they are determined to be Program Pass and are then set to be Program Inhibit. At this point, the threshold voltages of the memory cells set to be Program Inhibit are fixed in the distribution 70. Thus, the threshold voltages of the memory cells that must be programmed to data ‘0101’ are within the threshold voltage range corresponding to the data ‘0011’ (Vfy2≦Vth≦Vpre2). Thus, the memory cells included in the distribution 70 include memory cells that should be programmed to data ‘0101’ but instead have a threshold voltage corresponding to data ‘0011’, according to the programming of the fourth page data. Such memory cells have a 2-bit error as can be seen from the comparison of the data ‘0011’ and the data ‘0101’.
FIG. 2 illustrates a diagram of a problem of over-programming that may occur after programming, e.g., fourth page data.
Referring to FIG. 2, the threshold voltage of memory cells forms threshold voltage distributions 30 and 50 according to the programming of the third page data. The distribution 30 (or state 1) corresponds to 3-bit data ‘011’. The distribution 50 (or state 2) corresponds to 3-bit data ‘101’. By the programming of the fourth page data, memory cells included in the distribution 30 have a threshold voltage of one of the distributions 30 and 40. By the programming of the fourth page data, normal memory cells included in the distribution 50 have a threshold voltage of one of the distributions 50 and 60. The threshold voltage distribution 40 resulting from the programming of the fourth page data may be created in the form of a threshold voltage distribution 45 by the over-programmed memory cells. The threshold voltage distribution 45 includes a first verify voltage Vpre2 for verifying the programming to the threshold voltage distribution 40, and a threshold voltage distribution 80 exceeding over a second verify voltage Vfy2. Memory cells corresponding to the distribution 80 are memory cells that must be programmed to data ‘0011’. However, the memory cells corresponding to the distribution 80 is not set to be Program Inhibit by the program verify operation of the fourth page data. Rather, the memory cells included in the distribution 80 are misinterpreted as memory cells included in the distribution 50, and thus, may be programmed to the threshold voltage distribution 60 corresponding to data ‘0101’.
As described with reference to FIGS. 1 and 2, a memory cell may have at least 2-bit error due to charge loss or over-programming after the program operation of the fourth page data. Such an error causes a large load on a memory device that performs a read operation (fractional read) using a relative interval from a reference value of the threshold voltage distribution (e.g., an average value of the distribution). Such an error, e.g., a 2-bit error, may cause a load on error correction in a read operation. Even an error smaller than the 2-bit error may cause a large load on a read operation that is performed based on soft decision, when the threshold voltage resulting from the program operation has a relatively large interval.
As described above, the memory cells in the multi-bit flash memory device should be controlled to have a small interval between threshold voltage distributions corresponding to the data to be stored. A step size of a program voltage may be reduced for the dense threshold voltage distribution, but a reduction in the step size greatly reduces a programming speed.
A technique(s) for solving the limitations due to problems such as, e.g., charge loss and over-programming in the multi-bit flash memory device with a dense threshold voltage distribution is/are required.